1. Field of the Invention
The present invention relates to a circuit for automatically adjusting duty cycle of a clock signal to be used in a logical circuit (hereinafter referred to as an automatic clock duty cycle adjusting circuit).
2. Prior Art
An arrangement of a prior art automatic clock duty cycle adjusting circuit will be now described with reference to FIG. 7. In FIG. 7, denoted at 21 is a T-type flip-flop (hereinafter referred to as a T-FF) and 22 is a variable delay circuit. An input clock signal 13 is connected to a clock terminal T of the T-FF 21. An inverse output which is output from an output terminal Q of the T-FF 21 is connected to a reset terminal RB of the T-FF 21 by way of the variable delay circuit 22. A set data 25 is given to the variable delay circuit 22 from an external device.
FIG. 8 is a timing chart showing an operation of the automatic clock duty cycle adjusting circuit of FIG. 7. FIG. 8(A) shows a waveform of the input clock signal 13, FIG. 8(B) shows a waveform of an output clock signal 14 of the T-FF 21 and FIG. 8(C) shows a waveform of an output 23 of the variable delay circuit 22.
In FIG. 7, when a leading edge of the input clock signal 13 of FIG. 8 (A) is input to the clock terminal T of the T-FF 21, the output clock signal 14 to be output from the output terminal Q of the T-FF 21 is changed from an "L" level to an "H" level as denoted at a in FIG. 8(B). The inverse output of the T-FF 21 is input to the reset terminal RB of the same while it is delayed by the variable delay circuit 22 by the time corresponding to the delay set data 25. As a result, the output of the T-FF 21 is changed from the "H" level to the "L" level as denoted at b in FIG. 8(B). In FIG. 8(C), the time corresponding to the delay set data 25 is T1.
As mentioned above, a positive pulse width of the output clock signal 14 is the sum of the delay time T1 of the variable delay circuit 22 and an operation delay time T2 which is taken from the reset terminal RB to the output terminal Q of the T-FF 21. Accordingly, when the delay time T1 of the variable delay circuit 23 is varied by the delay set data 25, the duty cycle of the output clock signal 14 is varied in response thereto. As a result, supposing that a period of the output clock signal 14 is T, the duty cycle is expressed as (T1+T2)T.times.100 (%).
However, there is the following drawback in the prior art automatic clock duty cycle adjusting circuit. In order to adjust the duty cycle of the output clock signal 14 by varying the time set data 25 of the variable delay circuit 22, it is necessary to vary the delay set data 25 of the variable delay circuit 22 while monitoring a waveform of the output clock signal 14 from the FF-21 by an oscilloscope, etc.